1. Field of the Invention
The present invention relates to nonvolatile programmable logic using integrated magnetic devices such as giant-magneto-resistance (GMR) or spin-dependent-tunneling (SDT) devices. Such programmable logic is useful for programmable logic circuits, adaptive computing systems, programmable analog circuits, magnetic random access memories, and control systems.
2. Problems in the Art
Programmable Logic Devices (PLDS) and Programmable Logic Arrays (PLAs) are widely used for inexpensive prototyping and small volume production runs of digital logic functions. Typically, the term xe2x80x98PLDxe2x80x99 is used to describe a relatively small device that can be used to realize perhaps a sum of products or customized state machine and where the program information is usually stored in some form of nonvolatile memory. The term, programmable logic array or PLA on the other hand, usually denotes a more complicated structure that may contain many thousands of equivalent gates but where the programming information is usually stored in a volatile program memory that must be loaded during power up. More recently, some versions of these programmable logic devices that have the capability of being rapidly reconfigured have also been shown useful in high performance and specialized computing.
A significant problem with PLAs, which are largely based upon RAM (random access memory)-like cells, is that the memory is lost upon loss of power. This is contrary to ROM (read only memory) where data is typically stored during manufacturing and is nonvolatile. A computer normally employs random access memory for fast storage of in-use programs or data, although in the case of PLAs it is used for storing the customized programming information.
Nonvolatile memory, besides magnetic disks and tapes, is not new in the art. Computer core memory itself was nonvolatile before the introduction of semi-conductor RAM in the early 1970""s. It was assembled from magnetic cores, which were fabricated out of magnetic ferrite materials. These transformer coils were tiny toroidal rings, which were threaded with fine copper wires. Current pulses through the wires would magnetize the cores at either right or left handed to store a 0 or a 1; and thus have a bipolar or binary memory element. Each core was a bit. However, this memory was slow and expensive and was low density by today""s standards.
In comparison, present semi-conductor RAM is relatively fast, relatively cheap to fabricate in large quantities, and relatively small. However, it is volatile. Similarly, most semi-conductor digital components, such as latches, counters, flip-flops, etc. have the above-mentioned advantages, yet are also volatile. There is a need for nonvolatile components of this type. Further, regardless of non-volatility, there is room in the art with respect to RAM or other digital logic components that are further reduced in size, speedier, more reliable, and can be operated by and consume less power.
Attempts have been made to use magnetic principles (nonvolatile) as a method of storing binary information. An example is experimentation with anisotropic magnetoresistance (AMR) using one or more layers of AMR magnetic film. Localized portions of the material are magnetized in different directions to store the binary information.
The Giant Magnetoresistance Effect (GMR) results in larger changes in resistance in response to small magnetic fields in certain layered materials than are typically observed with the AMR effect. The GMR effect and a general explanation thereof are discussed in Prinz, Gary A., xe2x80x9cMagnetoelectronics,xe2x80x9d Science 282, 1660 (1998), incorporated by reference herein. Depending on the magnetism relative to spin polarization of current, the GMR material can be more or less conductive for electrons of specific spin polarization.
It has been shown that the magnetic field generated by even small currents could thus xe2x80x9cprogramxe2x80x9d a GMR component to several xe2x80x9clogic states,xe2x80x9d i.e. higher resistance or lower resistance. Thus, it would be possible to xe2x80x9csensexe2x80x9d the logic state by sending current through the programmed GMR component and deriving its resistance (i.e. whether it is the higher or lower resistance). This produces a bipolar memory element that has the advantages of low power read or write, non-volatility, and self-contained. Also, importantly, there are no limitations to the number of read/write cycles known and both reading and writing can be done at high speeds; higher than most existing nonvolatile latches or memory elements.
Spin-polarized tunneling or spin dependant tunneling (SDT) is discussed at Bobo et al., xe2x80x9cSpin dependent tunneling junctions with hard magnetic layer pinningxe2x80x9d, J.Appl.Phys. 83, 6685 (1998), incorporated by reference herein, as another example of a possible magnetic device. In memory applications, SDT devices may be preferable to GMR devices in that they typically have a larger signal and higher intrinsic resistance for small area components.
However, the mere fact that GMR effect or SDT have been pointed out as a possible memory element is not sufficient for their effective implementation and use in an actual programmable logic circuit, where not only must data be stored in the device but also efficiently retrieved with a minimum of sensing circuitry. To perform adequately, the memory element must not only be programmable or writeable to at least two states; the different states must be reliably readable by the system. Further, it is important that the memory element be able to reliably withstand multiple, and preferably unlimited, read and/or write cycles. There is presently no known nonvolatile memory scheme that satisfactorily meets these criteria in such programmable logic circuits.
There have been some attempts to create nonvolatile, solid state latches or memory elements that improve over the state of the art. Some of the problems with these attempts are as follows. Many of such components require significant write energy. They have limitations regarding read/write speed and number of read/write cycles.
One specific example is called NVRAM or non-volatile random access memory (e.g. from Xicor). It is relatively large in that it actually consists of both a volatile conventional RAM memory and a similarly sized nonvolatile memory that is written with the contents of the volatile RAM during a power failure. In order to have energy to perform this writing of the non-volatile memory, it usually requires an external capacitor. In order to restore the state of NVRAM to what existed prior to power-down, the non-volatile memory is read upon the restoration of power and transferred to the conventional RAM. Because of the dual-memory configuration and the external component, this architecture is not conducive to large scale RAM and the like. Similarly, most PLD devices employ some form of nonvolatile programming technology that may not be changed after it is initially programmed or that may require many microseconds or milliseconds of time to reprogram. Most of these latter types of devices can also only be programmed a limited number of times because repeated programming eventually harms the device.
Programmable logic circuits have evolved since the 1970""s. These circuits have revolutionized digital prototyping and design by offering cost effective and rapid hardware solutions to complex digital design problems that now routinely exceed 100K equivalent gates per chip. Historically, these circuits have employed digital memory cells that defined user programmable logic blocks (usually via look-up tables (LUTs)) and customized interconnects between the logic blocks. In traditional implementations of these circuits, the program memory would be changed only in the process of debugging the design and would thereafter be fixed in each chip. In the most advanced forms of field programmable logic circuits (FPGAs), static complementary metal-oxide-semiconductor (CMOS) registers or static random-access memory (SRAM) are used to define the various LUTs and associated interconnects. Because this memory is volatile, any loss of power will require that they be reinitialized into the desired state, usually via an external nonvolatile memory. On-chip nonvolatile alternatives to CMOS memory, such as antifuse or EEPROM, inevitably have other drawbacks. Antifuse methods, whereby a short is intentionally made between on-chip interconnect lines, is inherently a one-time process that is generally not accomplished in its original place. While EEPROM methods are generally reversible, at least up to some number of cycles, writing is typically very slow (often on the order of milliseconds) and specialized on-chip circuitry may be required to write the memory cells.
An interesting variation on the use of FPGAs is in reconfigurable computing. In this application the FPGA program information is changed on the fly to achieve, in some cases, significantly improved computational results. The primary limitation to fruitfully employing these reconfigurable structures is the time required in reprogramming the circuit from one state to another. For example, in FPGA architectures not specifically designed for rapid reprogramming, such as a commonly employed shift register based programming scheme, changing even a single bit will require reprogramming the entire array. This I/O bottleneck continues to be a problem even on more sophisticated arrays forcing the designer to employ bank switching or some similar method that does not actually reuse the programmable logic so much as merely select one portion at a time.
It is therefore a primary object of the present invention to improve over the problems and deficiencies in the art, relevant to nonvolatile programmable logic.
Another object of the present invention is to provide state storage or logic information that is nonvolatile.
Further objects, features and advantages of the present invention include an apparatus and method for a nonvolatile programmable logic, which has:
a) low write energy;
b) an unlimited number of read/write cycles;
c) the entire function can be included on-chip, and therefore no off-chip components are needed;
d) the capability of rapidly reconfiguring significant portions or even the entire programmable logic device in a very short period of time;
e) circuitry that is easier to manufacture;
f) low power dissipation;
g) fast response time; and
h) significant flexibility.
These and other objects, features, and advantages of the invention will become more apparent with further reference to the specification and claims.
The invention is programmable logic using what are referred herein to generally as integrated magnetic devices, e.g., giant-magnetoresistance (GMR) or spin-dependent-tunneling (SDT) devices. Magnetic-based data storage can be programmed using an on-chip current generated magnetic field. In latch form, the circuit relies on the integrated magnetic devices, as the fundamental data storage unit.
The invention includes a variety of aspects of programmable logic. In first and second aspects, using magnetic devices configured in the form of a latch cell, the state of magnetic devices may be used to open or close switches or define the contents of look-up tables used within programmable logic. In the third aspect the magnetic components are programmed in pairs (consisting of an evaluation and reference device) and placed in series under or over the input current lines. Together, the relative resistance of the evaluation string and the reference string define the logical output of the circuit with the logical function determined by the programming of the magnetic devices.
Resistance of the integrated magnetic device can be programmed to higher or lower values with an on-chip current generated field. This higher or lower resistance can then be sensed and translating to high or low states (binary states) in the circuit. It can be used as long or short-term data storage without electrical power support. It does not have an inherent limitation on the number of read/write cycles.